1. Field of the Invention
The present invention relates to an information processing system to realize highly reliable data processing by control of data flow to a plurality of data processing units.
2. Description of the Related Art
Conventionally, a method of dividing entire data processes into predetermined functions as hardware processes, and performing the series of data processes as pipe-line processes by connecting the hardware modules in the order of the process flow to realize a series of data processing such as print image processing quickly and efficiently, is known.
On the other hand, image processing can be efficiently realized by changing the order of series of processing. For example, when an image is output to an output device having a predetermined number of pixels, resolution conversion is required for coordination of number of pixels or resolution. When the number of pixels of an input image is larger than that of the output device, it is better to perform resolution conversion on the upstream side of the processing to reduce the number of pixels and then perform the processing. However, when the number of pixels of the input image is smaller than that of the output device, it is better to perform the processing without resolution conversion, on the image with the small number of pixels, and then perform the resolution conversion immediately before output on the downstream side of the processing.
Further, for example, in a case where conversion from certain space (e.g. input device space) to standard space (e.g. resolution 600 dpi CIELAB color space) is performed then processing is performed to convert the space to another space (e.g. output device space), the processing order of space converters on the input side and the output side (the processing order of one-dimensional LUT, matrix operation, three-dimensional LUT and the like) is inverted. That is, when the processing order can be changed, the same processing module can be shared on the input and output sides. However, in the above-described data processing method, the processing order cannot be changed. Accordingly, for example, as plural modules having the same function are provided so as to change the processing order, wasteful modules exist.
To solve the above-described problem, Japanese Patent Laid-Open No. 01-023340 proposes a method of connecting respective processing modules with a ring-shaped network. According to this method, by changing data connection destination on the ring network, the processing order can be changed.
Further, “dead lock” means a condition where input into processing modules cannot be performed and the ring bus is occupied with data packets. Japanese Patent Laid-Open No. 01-023340 proposes providing a queue to temporarily hold data packets in this dead lock condition. That is, first, empty space is temporarily ensured on the ring bus after the occurrence of dead rock condition. Then, by enabling transmission of a data packet which can be inputted into a processing module which has been hindered by the bus occupation, processing on the ring bus can be continued.
However, in the above-described conventional method, there is an upper limit in the length (amount) of the queue temporarily validated in the dead lock condition. Accordingly, although the dead lock condition can be avoided regarding such assumed occupation status, another occupation status beyond assumption that continues after the temporary queue validation may occur. At this time, even though a temporary queue is used, a data packet that cannot be inputted module into a processing at some future time may occur. In such case, the unprocessed data packet occupies the ring bus and a dead lock condition occurs again. Further, in this case, as it is necessary to prepare a temporary queue having a constant amount to avoid a dead lock condition, the circuitry scale of a data processing unit is unnecessarily increased.